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Abstract:
Many high-level synthesis tools offer degrees of freedom in mapping high-level specifications to Register-Transfer Level descriptions. These choices do not affect the functional behavior but span a design space of different cost-performance tradeoffs. In this paper we present a novel machine learning-based approach that efficiently determines the Pareto-optimal designs while only sampling and synthesizing a fraction of the design space. The approach combines three key components: (1) A regression model based on Gaussian processes to predict area and throughput based on synthesis training data. (2) A "smart" sampling strategy, GP-PUCB, to iteratively refine the model by carefully selecting the next design to synthesize to maximize progress. (3) A stopping criterion based on assessing the accuracy of the model without access to complete synthesis data. We demonstrate the effectiveness of our approach using IP generators for discrete Fourier transforms and sorting networks. However, our algorithm is not specific to this application and can be applied to a wide range of Pareto front prediction problems.
Reference:
''Smart'' Design Space Sampling to Predict Pareto-Optimal Solutions M. Zuluaga, A. Krause, P. A. Milder, M. PüschelIn Proc. Languages, Compilers, Tools and Theory for Embedded Systems (LCTES), 2012Best Paper Award Nominee
Bibtex Entry:
@inproceedings{zuluaga12smart,
	Author = {Marcela Zuluaga and Andreas Krause and Peter A. Milder and Markus P{\"u}schel},
	Booktitle = {Proc. Languages, Compilers, Tools and Theory for Embedded Systems (LCTES)},
	Doi = {10.1145/2248418.2248436},
	Title = {''Smart'' Design Space Sampling to Predict Pareto-Optimal Solutions},
	Year = {2012}}